Modern integrated circuit chips comprise a plurality of input and output terminals (I/O) which have to be arranged on the limited plane of the chip or substrate size. This increasing plurality of I/O terminals must be connected to surrounding electronic components. Commonly the chips are directly connected to other chips or electronic components or are arranged on a chip carrier or a substrate which comprises wiring lines for interconnecting the chips.
The chip packaging structure of the present invention utilizes a multilayer substrate having several conductive planes separated by insulating layers. The substrates can be made of ceramic or silicon. Silicon carriers are preferred because of the similar manufacturing techniques in the chip production. Further, the thermal expansion coefficients are equal. A silicon substrate is disclosed in U.S. Pat. No. 4,866,507 (EP-A2-0 246 458) with further prior art references.
A well known technique for connecting the chip to a carrier is the controlled collapse chip connection (C-4) technique which allows a plurality of I/O's to be close together. This technique is disclosed in the U.S. Pat. No. 3,401,126 and U.S. Pat. No. 3,429,040. For the application of this technique the corresponding terminals of the carrier have to be precisely prepared with a contact layer which limits the size of the contact ball (ball limiting layer) and provides sufficient contact with the terminals of the carrier. Additionally, a solder stop layer can be necessary if the terminal is connected to wiring lines on the surface of the substrate. Commonly the substrate comprises on additional metallization plane which only serves for the connection of the chip by the C-4 technique.
Another well-known technique for packaging chips or carriers is the tape automated bonding (TAB) technique. TAB packaging involves the use of a web of material, generally called a carrier tape, to carry electrically conductive leads which provide connections between the chip and the outside world. An inner cluster of the conductive leads is bonded to the connecting pads of the chips or the substrate. The outer cluster is severed from the tape, and the outer leads of the tape/chip or tape/carrier combination, respectively, are bonded to conductive pads residing on an underlying circuit board. This method as well as the wire-bonding technique allows no such plurality of I/O's as the C-4 technique. Both techniques imply a bump which is usually made of gold or of gold/copper and formed on the integrated circuits or on the carriers. There are several processes just for the purpose of forming these bumps on conductors, and they are well known to those skilled in the art. The bumps are relatively thick in comparison with usual layer dimensions. Further, the bumps need a contact layer for the connection with the metallization plane in the chip or carrier. The bumps are deposited by an electro-plating process, which requires an uninterrupted conductive layer over the carrier surface for uniform current distribution during electro-plating. It is called seed layer.
In order to allow the packaging of integrated circuit chips having a high density of I/O's and to reduce manufacturing costs, carriers, preferably silicon carriers, comprising terminals for C-4 connections and TAB or wire-bonding connections are necessary.
Thus, the invention as claimed solves the problem of providing an integrated circuit chip packaging structure and a method for manufacturing such a structure with high accuracy and a minimum of manufacturing steps.